text.skipToContent text.skipToNavigation


Ultra Low-Noise and Low Power JESD204B Compliant Clock Jitter Cleaner


Package | PIN: ZCR | 144
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $23.44
10-24 $21.80
25-99 $21.04
100-249 $18.37
250-499 $17.49
500-749 $16.09
750-999 $14.45
1000+ $14.40


  • Dual Loop PLL Architecture
    • 65-fs RMS Jitter (10 kHz to 20 MHz)
    • 85-fs RMS Jitter (100 Hz to 20 MHz)
    • –165-dBc/Hz Noise Floor at 122.88 MHz
  • JESD204B Support
    • Single Shot, Pulsed, and Continuous SYSREF
  • 16 Differential Output Clocks in 8 Frequency Groups
    • Programmable Output Swing Between 700 mVpp to 1600 mVpp
    • Each Output Pair Can be Configured to SYSREF ClockOutput
    • 16-Bit Channel Divider
    • Minimum SYSREF Frequency of 25 kHz
    • Maximum Output Frequency of 2 GHz
    • Precision Digital Delay, Dynamically Adjustable
      • Digital Delay (DDLY) of ½ × Clock Distribution Path Frequency (2 GHz Maximum)
    • 60-ps Step Analog Delay
    • 50% Duty Cycle Output Divides, 1 to 65535
      (Even and Odd)
  • 4 Reference Inputs
    • Holdover Mode, When Inputs are Lost
    • Automatic and Manual Switch-Over Modes
    • Loss-of-Signal (LOS) Detection
  • 1.05-W Typical Power Consumption With 16 Outputs Active
  • Operates Typically From a 1.8-V (Outputs, Inputs) and 3.3-V Supply (Digital, PLL1, PLL2_OSC, PLL2 Core)
  • Fully Integrated Programmable Loop Filter
  • PLL2
    • PLL2 Phase Detector Rate Up to 250 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO
  • Internal Power Conditioning: Better Than –80dBc PSRR on VDDO for 122.88-MHz Differential Outputs
  • 3- or 4-Wire SPI Interface (4-Wire is Default)
  • –40ºC to +85ºC Industrial Ambient Temperature
  • Supports 105ºC PCB Temperature (Measured at Thermal Pad)
  • LMK04616: 10-mm × 10-mm NFBGA-144 Package With 0.8-mm Pitch

All trademarks are the property of their respective owners.

Texas Instruments  LMK04616ZCRR

The LMK0461x device family is the industry’s highest performance andlowest power jitter cleaner with JESD204B support. The 16 clock outputs can be configured to driveeight JESD204B converters or other logic devices using device and SYSREF clocks. The 17th outputcan be configured to provide a signal from PLL2 or a copy from the external VCXO.

Features like fully integrated PLL1 and PLL2 loop filters, a high numberof integrated LDOs, digital and analog delay, the flexibility to supply outputs with 3.3V, 2.5V and1.8V as well as the option to generate multiple SYSREF domains simultaneously makes the device easyto use.

Not limited to JESD204B applications each of the 17 outputs can beconfigured for traditional clocking systems.