|Package | PIN:||SIA | 8|
|Temp:||I (-40 to 85)|
- Ultra-Low Noise, High Performance
- Jitter: 500-fs RMS Typical fOUT > 50 MHz onLMK61E0M
- LMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHz
- Total Frequency Tolerance of ±25 ppm
- System Level Features
- Glitch-Less Frequency Margining: Up to ±1000 ppm FromNominal
- Internal EEPROM: User Configurable Start-Up Settings
- Other Features
- Device Control: Fast Mode I2C up to 1000kHz
- 3.3-V Operating Voltage
- Industrial Temperature Range(–40ºC to +85ºC)
- 7-mm × 5-mm 8-Pin Package
- Default Frequency: 70.656 MHz
All trademarks are the property of their respective owners.
Texas Instruments LMK61E0M-SIAT
The LMK61E0 family of ultra-low jitter PLLatinumTMprogrammable oscillators use fractional-N frequency synthesizers with integrated VCOs to generatecommonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device featuresself start-up from on-chip EEPROM to generate a factory programmed default output frequency, or thedevice registers and EEPROM settings are fully programmable in-system throughI2C serial interface. The device provides fine and coarse frequencymargining control through I2C serial interface, making it adigitally-controlled oscillator (DCXO).
The PLL feedback divider can be updated to adjust the output frequency without spikes orglitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) forcompatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (Rdivider=1, doubler enabled) for compatibility with broadcast video requirements. The frequencymargining features also facilitate system design verification tests (DVT), such as standardscompliance and system timing margin testing.