|Package | PIN:||PW | 28|
|Temp:||S (-25 to 85)|
- Register-Selectable Audio-Processing Functions up to 48-kHz fS
- Dynamic Range Control(DRC)
- DAC Functionality to 384-kHz fS
- Market-Leading Low Out-of-Band Noise
- Selectable Digital-Filter Latency and Performance
- No DC-Blocking Capacitors Required
- Integrated Negative Charge Pump
- Intelligent Muting System; Soft Up or Down Ramp and Analog Mute for 120-dB Mute SNR
- Integrated High-Performance Audio PLL With BCK Reference to Generate SCK Internally
- Accepts 16-, 20-, 24-, and 32-Bit Audio Data
- PCM Data Formats: I2S, Left-Justified, Right-Justified, TDM / DSP
- SPI or I2C Control
- Software or Hardware Configuration
- Automatic Power-Save Mode When LRCK and BCK are Deactivated
- 1.8-V or 3.3-V Failsafe LVCMOS Digital Inputs
- Single Supply Operation:
- 3.3-V Analog, 1.8-V or 3.3-V Digital
- Integrated Power-On Reset
- Small28-Pin Package
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Texas Instruments PCM5122PW
The PCM512x devices are a family of monolithic CMOS-integratedcircuits that include a stereo digital-to-analog converter and additional support circuitry in asmall TSSOP package. The PCM512x uses the latest generation of TI’s advancedsegment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clockjitter.
Members of the PCM512x family integrate preset audio processingfunctions with programmable coefficients, allowing developers to change the characteristics of theinterpolation filter, speaker EQ, dynamic range controls, and average volume control in theirproducts.
The PCM512x provides 2.1-VRMS ground-centeredoutputs, allowing designers to eliminate DC-blocking capacitors on the output, as well as externalmuting circuits traditionally associated with single supply line drivers.
The integrated line driver surpasses all other charge-pump-based line drivers bysupporting loads down to 1 kΩ. By supporting loads down to 1 kΩ, the PCM512xcan essentially drive up to 10 products in parallel (LCD TV, DVDR, AV receivers, and so forth).
The integrated PLL on the device removes the requirement for a system clock (commonlyknown as master clock), allowing a 3-wire I2S connection, along withreducing system EMI.