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Single-channel MIPI® DSI to single-link LVDS bridge & FlatLink™ integrated circuit


Package | PIN: ZQE | 64
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $3.61
10-24 $3.25
25-99 $3.02
100-249 $2.65
250-499 $2.48
500-749 $2.11
750-999 $1.78
1000+ $1.70


  • Implements MIPI® D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
  • Single Channel DSI Receiver Configurable for 1, 2, 3, or 4 D-PHY Data Lanes Per Channel Operating up to 1 Gbps/Lane
  • Supports 18 bpp and 24 bpp DSI Video Packets With RGB666 and RGB888 Formats
  • Max Resolution up to 60 fps WUXGA
    1920 × 1200 at 18 bpp and 24 bpp Color With Reduced Blanking. Suitable for 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp
  • FlatLink™ Output for Single-Link LVDS
  • Supports Single Channel DSI to Single-Link LVDS Operating Mode
  • LVDS Output Clock Range of 25 MHz to 154 MHz
  • LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
  • 1.8-V Main VCC Power Supply
  • Low Power Features Include Shutdown Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
  • LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
  • ESD Rating ±2 kV (HBM)
  • Packaged in 64-pin 5-mm × 5-mm BGA MICROSTAR JUNIOR (ZQE)
  • Temperature Range: –40°C to 85°C

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Texas Instruments  SN65DSI83ZQER

The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI D-PHY receiverfront-end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum inputbandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets andconverts the formatted video data stream to a FlatLink-compatible LVDS output operating at pixelclocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes perlink.

The SN65DSI83 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24bpp with reduced blanking. The SN65DSI83 device is also suitable for applications using 60 fps 1366× 768 / 1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate thedata stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI83 device is compatiblewith a wide range of microprocessors, and is designed with a range of power management featuresincluding low-swing LVDS outputs, and the MIPI defined ultra-low power state (ULPS) support.

The SN65DSI83 device is implemented in a small outline 5-mm × 5-mm BGA MICROSTAR JUNIORat 0.5-mm pitch package, and operates across a temperature range from –40ºC to 85ºC.