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SN65DSI84ZQER

MIPI® DSI bridge to FlatLink™ LVDS single-channel DSI to dual-link LVDS bridge

Packaging

Package | PIN: ZQE | 64
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $3.85
10-24 $3.47
25-99 $3.24
100-249 $2.90
250-499 $2.71
500-749 $2.36
750-999 $2.04
1000+ $2.00

Features

  • Implements MIPI® D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
  • Single Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
  • Supports 18 bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
  • Suitable for 60-fps WUXGA 1920 × 1200 Resolution at 18-bpp and 24-bpp Color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
  • FlatLink™ Output Configurable for Single-Link or Dual-Link LVDS
  • Supports Single Channel DSI to Dual-Link LVDS Operating Mode
  • LVDS Output Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Modes
  • LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
  • 1.8-V Main VCC Power Supply
  • Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
  • LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
  • ESD Rating ±2 kV (HBM)
  • Packaged in 64-pin 5-mm × 5-mm BGA (ZQE)
  • Temperature Range: –40°C to 85°C

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Texas Instruments  SN65DSI84ZQER

The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiverfront-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum inputbandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets andconverts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixelclocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS interface withfour data lanes per link.

The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatchbetween the DSI and LVDS interfaces.

Designed with industry compliant interface technology, the SN65DSI84 is compatible with awide range of micro-processors, and is designed with a range of power management features includinglow-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI84 is implemented in a small outline 5x5mm BGA at 0.5 mm pitch package, andoperates across a temperature range from -40ºC to 85ºC.