SN65DSI85TPAPRQ1

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SN65DSI85TPAPRQ1

Automotive Dual Channel MIPI DSI to Dual-Link Flatlink LVDS Bridge

Packaging

Package | PIN: PAP | 64
Temp: T (-40 to 105)
Carrier: Cut Tape
Qty Price
1-9 $11.09
10-24 $9.97
25-99 $9.32
100-249 $8.35
250-499 $7.80
500-749 $6.78
750-999 $5.87
1000+ $5.75

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient OperatingTemperature
    • Device HBM ESD Classification Level 3A
    • DeviceCDM ESD Classification Level C6
  • Implements MIPI D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
  • Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
  • Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
  • Suitable for 60-fps WQXGA 2560 × 1600 Resolution at 18-bpp and 24-bpp Color, and 60 fps (120 fps Equivalent) WUXGA 1920 × 1200 Resolution With 3D Graphics at 24-bpp Color
  • MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configurations
  • Output Configurable for Single-Link or Dual-Link LVDS
  • Supports Dual-Channel DSI ODD or EVEN and LEFT or RIGHT Operating Modes
  • Supports Two Single-Channel DSI to Two Single-Link LVDS Operating Mode
  • LVDS Output-Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Mode
  • LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
  • 1.8-V Main VCC Power Supply
  • Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
  • LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
  • Packaged in 64-pin 10 mm × 10 mm HTQFP (PAP) PowerPAD™ IC Package

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Texas Instruments  SN65DSI85TPAPRQ1

The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHYreceiver front-end
configuration with four lanes per channel operating at 1 Gbps per lane and a maximum inputbandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets andconverts the formatted video data-stream to an LVDS output operating at pixel clocks operating from25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaceswith four data lanes per link.

The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions atan equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented toaccommodate the data stream mismatch between the DSI and LVDS interfaces.

The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mmHTQFP package with a
0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.