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14.2Gbps Quad Mux, Linear-Redriver with Signal Conditioning


Package | PIN: ZJA | 167
Temp: I (-40 to 85)
Carrier: Partial Tray
Qty Price
1-9 $26.77
10-24 $25.03
25-99 $24.24
100-249 $21.54
250-499 $21.38
500-749 $20.12
750-999 $18.06
1000+ $18.00


  • Quad 2:1 Mux and 1:2 Demux
  • Multi-Rate Operation up to 14.2 Gbps Serial Data
  • Linear Receiver Equalization Which Increases
    Margin at System Level of Decision Feedback
  • Bandwidth: 18 GHz, Typical
  • Per-Lane P/N Pair Inversion
  • Port or Single Lane Switching
  • Low Power: 150 mW/Channel, Typical
  • Loopback Mode on All Three Ports
  • I2C Control in Addition to GPIO
  • DIAG Mode That Outputs Data of Line Side Port
    to Both Fabric Side Ports
  • 2.5-V or 3.3-V Single Power Supply
  • PBGA Package 12-mm × 12-mm × 1-mm, 0.8-mm
    Terminal Pitch
  • Excellent Impedance Matching to 100-Ω PCB
    Transmission Lines
  • Small Package Size Provides Board Real Estate
  • Adjustable Output Swing Provides Flexible EMI
    and Crosstalk Control
  • Low Power
  • Supports 10GBASE-KR Applications With Ability
    to Transparency for Link Training

Texas Instruments  SN65LVCP114ZJA

The SN65LVCP114 device is an asynchronous, protocol-agnostic, low-latency QUAD mux, linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device linearly compensates for channel loss in backplane and active-cable applications. The architecture of SN65LVCP114 linear-redriver is designed to work effectively with ASIC or FPGA products implementing digital equalization using decision feedback equalizer (DFE) technology. The SN65LVCP114 mux, linear-redriver preserves the integrity (composition) of the received signal, ensuring optimum DFE and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver solution while at the same time extending the effectiveness of DFE.

SN65LVCP114 is configurable through GPIO or an I2C interface.

A single 2.5-V or 3.3-V power supply supports the operation of the SN65LVCP114.

The SN65LVCP114 is packaged in a 12-mm × 12-mm × 1-mm PBGA package with 0.8-mm pitch.

The SN65LVCP114 has three ports; each port is a quad lane. The switch logic of SN65LVCP114 can be implemented to support a 2:1 MUX per lane, 1:2 DEMUX per lane, and independent lane switching. The receive equalization can be independently programmed for each of the ports. The SN65LVCP114 supports loopback on all three ports.