SN65LVDS16DRFT

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SN65LVDS16DRFT

2.5-V/3.3-V Oscillator Gain Stage/Buffer with Enable

Packaging

Package | PIN: DRF | 8
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $4.61
10-24 $4.15
25-99 $3.87
100-249 $3.47
250-499 $3.24
500-749 $2.82
750-999 $2.44
1000+ $2.39

Features

  • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
  • Clock Rates to 2 GHz
    • 140-ps Output Transition Times
    • 0.11 ps Typical Intrinsic Phase Jitter
    • Less than 630 ps Propagation Delay Times
  • 2.5-V or 3.3-V Supply Operation
  • 2-mm × 2-mm Small-Outline No-Lead Package
  • APPLICATIONS
    • PECL-to-LVDS Translation
    • Clock Signal Amplification

Texas Instruments  SN65LVDS16DRFT

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.

The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx17 defaults to 575 mV as well.

Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.