SN65LVDS302ZQER

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SN65LVDS302ZQER

Programmable 27-Bit Display Serial Interface Receiver

Packaging

Package | PIN: ZQE | 80
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $4.72
10-24 $4.25
25-99 $3.96
100-249 $3.47
250-499 $3.25
500-749 $2.76
750-999 $2.33
1000+ $2.23

Features

  • Serial Interface Technology
  • Compatible With FlatLink™3G such as
    SN65LVDS301
  • Supports Video Interfaces up to 24-bit RGB Data
    and 3 Control Bits Received over 1, 2 or 3
    SubLVDS Differential Lines
  • SubLVDS Differential Voltage Levels
  • Up to 1.755-Gbps Data Throughput
  • Three Operating Modes to Conserve Power
    • Active mode QVGA: 17 mW
    • Typical Shutdown: 0.7 µW
    • Typical Standby Mode: 27 µW Typical
  • Bus-Swap Function for PCB-Layout Flexibility
  • ESD Rating > 4 kV (HBM)
  • Pixel Clock Range of 4 MHz to 65 MHz
  • Failsafe on all CMOS Inputs
  • Packaged in 5-mm × 5-mm MicroStar Junior
    µBGA® With 0.5-mm Ball Pitch
  • Very low EMI meets SAE J1752/3 ′Kh′-spec

Texas Instruments  SN65LVDS302ZQER

The SN65LVDS302 receiver de-serializes FlatLink™3G compliant serial input data to 27 parallel data outputs. The SN65LVDS302 receiver contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the Channel Parity Error (CPE) output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly-received pixel. Instead, the last data word is held on the output bus for another clock cycle.