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QVGA-HVGA 27-Bit Display Serial Interface Transmitter


Package | PIN: ZQE | 80
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $3.74
10-24 $3.36
25-99 $3.13
100-249 $2.74
250-499 $2.57
500-749 $2.19
750-999 $1.85
1000+ $1.76


  • FlatLink™3G Serial-Interface Technology
  • Compatible With FlatLink3G Receivers Such as SN65LVDS306
  • Input Supports 24-bit RGB Video Mode Interface
  • 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit, and 2 Reserved Bits Transmitted Over One Differential Line
  • SubLVDS Differential Voltage Levels
  • Effective Data Throughput up to 405 Mbps
  • Three Operating Modes to Conserve Power
    • Active-Mode QVGA 17.4 mW (Typical)
    • Shutdown Mode 0.5 µA (Typical)
  • Bus Swap for Increased PCB Layout Flexibility
  • 1.8-V Supply Voltage
  • ESD Rating > 2 kV (HBM)
  • Typical Application: Host-Controller to Display-Module Interface
  • Pixel Clock Range of 4 MHz-15 MHz
  • Failsafe on all CMOS Inputs
  • Packaging: 80-Terminal 5-mm × 5-mm µBGA®

FlatLink is a trademark of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc.

Texas Instruments  SN65LVDS305ZQER

The SN65LVDS305 serializer device converts 27 parallel data inputs to one sub-low-voltage differential signaling (SubLVDS) serial output. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30 times the pixel-clock data rate. A copy of the pixel clock is output on a separate differential output.

FPC cabling typically interconnects the SN65LVDS305 with the display. Compared to parallel signaling, the SN65LVDS305 outputs reduce the EMI of the interconnect by over 20 dB.

The SN65LVDS305 supports three power modes (shutdown, standby and active) to conserve power. When transmitting, the PLL locks to the incoming pixel clock, PCLK, and generates an internal high-speed clock at the line rate of the data lines. The parallel data are latched on the rising or falling edge of PCLK, as selected by the external control signal CPOL. The serialized data is presented on the serial output, D, together with a recreated PCLK generated from the internal high-speed clock that is output on CLK. If PCLK stops, the device enters a standby mode to conserve power.

The parallel (CMOS) input bus offers a bus-swap feature. The SWAP terminal configures the input order of the pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7]. G[0:7], R[0:7], VS, HS, DE. This gives a PCB designer the flexibility to better match the bus to the host controller pinout or to put the transmitter device on the top side or the bottom side of the PCB.

The TXEN input can be used to put the SN65LVDS305 in a shutdown mode. The SN65LVDS305 enters an active standby mode if the input clock, PCLK, stops. This minimizes power consumption without the need for controlling an external terminal. The SN65LVDS305 is characterized for operation over ambient air temperatures of -40°C to 85°C. All CMOS inputs offer failsafe to protect the input from damage during power up and to avoid current flow into the device inputs during power up. An input voltage of up to 2.165 V can be applied to all CMOS inputs while VDD is between 0 V and 1.65 V.