text.skipToContent text.skipToNavigation


QVGA-VGA 27-Bit Display Serial Interface Receiver


Package | PIN: ZQC | 48
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $3.29
10-24 $2.96
25-99 $2.76
100-249 $2.41
250-499 $2.26
500-749 $1.92
750-999 $1.62
1000+ $1.55


  • FlatLink 3G Serial Interface Technology
  • Compatible With FlatLink™ 3G Transmitters Such as SN65LVDS307
  • Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over Two Differential Data Lines
  • SubLVDS Differential Voltage Levels
  • Up to 810-Mbps Data Throughput
  • Three Operating Modes to Conserve Power
    • Active mode VGA 60 fps: 17 mW
    • Typical Shutdown: 0.7 µW
    • Typical Standby Mode: 67 µW Typical
  • ESD Rating > 4 kV (HBM)
  • Pixel-Clock Range of 8 MHz-30 MHz
  • Failsafe on all CMOS Inputs
  • 4-mm × 4-mm MicroStar Junior™ µBGA® Package With 0,5-mm Ball Pitch
  • Very Low EMI
    • Small Low-Emission Interface Between Graphics Controller and LCD Display
    • Mobile Phones and Smart Phones
    • Portable Multimedia Players

FlatLink, MicroStar Junior are trademarks of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc.

Texas Instruments  SN65LVDS308ZQCR

The SN65LVDS308 receiver deserializes FlatLink 3G-compliant serial input data to 27 parallel data outputs. The SN65LVDS308 receiver contains one shift register to load 30 bits from two serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If a parity error is detected, the data output bus disregards the newly received pixel. Instead, the last data word is held on the output bus for another clock cycle.

The serial data and clock are received via sub-low-voltage differential signalling (SubLVDS) lines. The SN65LVDS308 supports three operating power modes (shutdown, standby, and active) to conserve power.

When receiving, the PLL locks to the incoming clock, CLK, and generates an internal high-speed clock at the line rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The deserialized data is presented on the parallel output bus with a recreation of the pixel clock, PCLK, generated from the internal high-speed clock. If no input CLK signal is present, the output bus is held static with PCLK and DE held low, while all other parallel outputs are pulled high.

The F/S control input selects between a slow CMOS bus output rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher-load designs.

The RXEN input can be used to put the SN65LVDS308 in a shutdown mode. The SN65LVDS308 enters an active standby mode if the common-mode voltage of the CLK input becomes shifted to VDDLVDS (e.g., the transmitter releases the CLK output into high-impedance). This minimizes power consumption without the need of switching an external control pin. The SN65LVDS308 is characterized for operation over ambient air temperatures of -40°C to 85°C. All CMOS and SubLVDS signals are 2-V tolerant with VDD = 0 V. This feature allows powering up I/Os before VDD is stabilized.