|Package | PIN:||DGG | 56|
|Temp:||I (-40 to 85)|
- AEC-Q100 Qualified with:
- Temperature Grade 3: –40°C to 85°C
- HBM ESD Classification 3
- CDM ESD Classification C6
- LVDS Display Series Interfaces Directly to LCD
Display Panels With Integrated LVDS
- Package: 14-mm × 6.1-mm TSSOP
- 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
Directly to Low-Power, Low-Voltage Application
and Graphic Processors
- Transfer Rate up to 135 Mpps (Mega Pixel Per
Second); Pixel Clock Frequency Range 10 MHz to
- Suited for Display Resolutions Ranging From
HVGA up to HD With Low EMI
- Operates From a Single 3.3-V Supply and 170
mW (Typical) at 75 MHz
- 28 Data Channels Plus Clock in Low-Voltage TTL
to 4 Data Channels Plus Clock Out Low-Voltage
- Consumes Less Than 1 mW When Disabled
- Selectable Rising or Falling Clock Edge Triggered
- Support Spread Spectrum Clocking (SSC)
- Compatible with all OMAP™ 2x, OMAP™ 3x, and
DaVinci™ Application Processors
Texas Instruments SN65LVDS93AIDGGRQ1
The SN65LVDS93A-Q1 FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS94 and LCD panels with integrated LVDS receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93A-Q1 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.
The SN65LVDS93A-Q1 is characterized for operation over ambient air temperatures of –40°C to 85°C.