SN65MLVD080DGG

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SN65MLVD080DGG

8-Channel Half-Duplex M-LVDS transceiver

Packaging

Package | PIN: DGG | 64
Temp: I (-40 to 85)
Carrier: Partial Tube
Qty Price
1-9 $6.94
10-24 $6.24
25-99 $5.83
100-249 $5.23
250-499 $4.88
500-749 $4.25
750-999 $3.68
1000+ $3.60

Features

  • Low-Voltage Differential 30- Line Drivers and Receivers for Signaling Rates(1) Up to 250 Mbps; Clock Frequencies Up to 125 MHz
  • Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • –1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise
  • Bus Pins High Impedance When Driver Disabled or VCC ≤ 1.5 V
  • Independent Enables for each Driver
  • Bus Pin ESD Protection Exceeds 8 kV
  • Packaged in 64-Pin TSSOP (DGG)
  • M-LVDS Bus Power Up/Down Glitch Free
  • APPLICATIONS
    • Parallel Multipoint Data and Clock Transmission Via Backplanes and Cables
    • Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485
    • Cellular Base Stations
    • Central-Office Switches
    • Network Switches and Routers

(1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

Texas Instruments  SN65MLVD080DGG

The SN65MLVD080 and SN65MLVD082 provide eight half-duplex transceivers for transmitting and receiving Multipoint-Low-Voltage Differential Signals in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. The driver outputs have been designed to support multipoint buses presenting loads as low as 30- and incorporates controlled transition times to allow for stubs off of the backbone transmission line.

The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD080) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers (SN65MLVD082) implement a failsafe by using an offset threshold. In addition, the driver rise and fall times are between 1 and 1.5 ns, complying with the M-LVDS standard to provide operation at 250 Mbps while also accommodating stubs on the bus. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges. The M-LVDS standard allows for 32 nodes on the bus providing a high-speed replacement for RS-485 where lower common-mode can be tolerated or when higher signaling rates are needed.

The driver logic inputs and the receiver logic outputs are on separate pins rather than tied together as in some transceiver designs. The drivers have separate enables (DE) and the receivers are enabled globally through (RE)\. This arrangement of separate logic inputs, logic outputs, and enable pins allows for a listen-while-talking operation. The devices are characterized for operation from –40°C to 85°C.