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SN74ABTH182504APM

Scan Test Devices With 20-Bit Universal Bus Transceivers

Packaging

Package | PIN: PM | 64
Temp: I (-40 to 85)
Carrier: Partial Tray
Qty Price
1-9 $17.81
10-24 $16.56
25-99 $15.98
100-249 $13.96
250-499 $13.29
500-749 $12.23
750-999 $10.98
1000+ $10.94

Features

  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Members of the Texas Instruments WidebusTM Family
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • UBT TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
  • B-Port Outputs of 'ABTH182504A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • State-of-the-Art EPIC-IIB TM BiCMOS Design
  • One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency
  • SCOPE TM Instruction Set
    • IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
    • Parallel-Signature Analysis at Inputs
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Device Identification
    • Even-Parity Opcodes
  • Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

 

SCOPE, Widebus, UBT, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

 

Texas Instruments  SN74ABTH182504APM

The 'ABTH18504A and 'ABTH182504A scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM universal bus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA), clock-enable ( and ), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and is low, A-bus data is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active. When is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the , LEBA, , and CLKBA inputs.

In the test mode, the normal operation of the SCOPETM universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

 

Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count addressing scheme is useful.

Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.

The B-port outputs of 'ABTH182504A, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot.

The SN54ABTH18504A and SN54ABTH182504A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH18504A and SN74ABTH182504A are characterized for operation from -40°C to 85°C.

 

 

A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA\, LEBA, CLKENBA\, and CLKBA.

Output level before the indicated steady-state input conditions were established