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SN74AUC1G79DCKR

Single Positive-Edge-Triggered D-Type Flip-Flop

Packaging

Package | PIN: DCK | 5
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $0.22
10-24 $0.19
25-99 $0.17
100-249 $0.15
250-499 $0.13
500-749 $0.10
750-999 $0.08
1000+ $0.07

Features

  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 1.9 ns at 1.8 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±8-mA Output Drive at 1.8 V

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Texas Instruments  SN74AUC1G79DCKR

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-VVCC, but is designed specifically for 1.65-V to 1.95-VVCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferredto the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltagelevel and is not directly related to the rise time of the clock pulse. Following the hold-timeinterval, data at the D input can be changed without affecting the levels at the outputs.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using thedie as the package.

This device is fully specified for partial-power-down applications usingIoff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.