SN74AUP1G125DPWR

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SN74AUP1G125DPWR

Low-Power Single Bus Buffer Gate with 3-State Output

Packaging

Package | PIN: DPW | 5
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $0.28
10-24 $0.24
25-99 $0.22
100-249 $0.19
250-499 $0.17
500-749 $0.13
750-999 $0.10
1000+ $0.09

Features

  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    < 10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.6 ns Maximum at 3.3 V

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Texas Instruments  SN74AUP1G125DPWR

The SN74AUP1G125 bus buffer gate is a single line driver with a 3-stateoutput. The output is disabled when the output-enable (OE) input is high.This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down,OE must be tied to VCC through a pullup resistor; theminimum value of the resistor is determined by the current-sinking capability of the driver.