|Package | PIN:||DRL | 5|
|Temp:||I (-40 to 85)|
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption
(ICC = 0.9 µA Maximum)
- Low Dynamic-Power Consumption
(Cpd = 4 pF Typical at 3.3 V)
- Low Input Capacitance (CI = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot
< 10% of VCC
- Input-Disable Feature Allows Floating Input Conditions
- Ioff Supports Partial-Power-Down Mode Operation
- Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
- Wide Operating VCC Range of 0.8 V to 3.6 V
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.6 ns Maximum at 3.3 V
All trademarks are the property of their respective owners.
Texas Instruments SN74AUP1G125DRLR
The SN74AUP1G125 bus buffer gate is a single line driver with a 3-stateoutput. The output is disabled when the output-enable (OE) input is high.This device has the input-disable feature, which allows floating input signals.
To ensure the high-impedance state during power up or power down,OE must be tied to VCC through a pullup resistor; theminimum value of the resistor is determined by the current-sinking capability of the driver.