SN74AUP1G14DRLR

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SN74AUP1G14DRLR

Low-Power Single Schmitt-Trigger Inverter

Packaging

Package | PIN: DRL | 5
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $0.28
10-24 $0.25
25-99 $0.22
100-249 $0.19
250-499 $0.17
500-749 $0.13
750-999 $0.10
1000+ $0.09

Features

  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model(C101)
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.9 ns Maximum at 3.3 V

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Texas Instruments  SN74AUP1G14DRLR

The AUP family is TI’s premier solution to the industry’s low power needs inbattery-powered portable applications. This family assures a very low static and dynamic powerconsumption across the entire VCC range of 0.8 V to 3.6 V, resulting in anincreased battery life. This product also maintains excellent signal integrity (seeAUP – The Lowest-Power Family andExcellent Signal Integrity).

This device functions as an independent gate with Schmitt-trigger inputs, which allowsfor slow input transition and better switching-noise immunity at the input.

This device is fully specified for partial-power-down applications usingIoff. The Ioff circuitry disables the outputs whenthe device is powered down. This inhibits current backflow into the device which prevents damage tothe device.