|Package | PIN:||DGV | 24|
|Temp:||Q (-40 to 125)|
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 8000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
- VCC Isolation Feature – If Either VCC Input Is at GND, All I/O Ports Are in the High-Impedance State
- Ioff Supports Partial Power-Down Mode Operation
- Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.4-V to 3.6-V Power-Supply Range
- I/Os Are 4.6-V Tolerant
- Maximum Data Rates
- 170 Mbps (VCCA < 1.8 V orVCCB < 1.8 V)
- 320 Mbps (VCCA ≥ 1.8 V and VCCB ≥ 1.8 V)
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Texas Instruments SN74AVC8T245DGVR
This 8-bit noninverting bus transceiver uses two separate configurable power-supplyrails. The SN74AVC8T245 is optimized to operate withVCCA/VCCB set at 1.4 V to 3.6 V. The device isoperational with VCCA/VCCB as low as 1.2 V. The Aport is designed to track VCCA. VCCA accepts anysupply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB.VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows foruniversal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and3.3-V voltage nodes.
The SN74AVC8T245 is designed for asynchronous communication between data buses. Thedevice transmits data from the A bus to the B bus or from the B bus to the A bus, depending on thelogic level at the direction-control (DIR) input. The output-enable (OE)input can be used to disable the outputs so the buses are effectively isolated.
The SN74AVC8T245 is designed so that the control pins (DIR and OE)are supplied by VCCA.
The SN74AVC8T245 solution is compatible with a single-supply system and can be replacedlater with a 245 function, with minimal printed circuit board redesign.
This device is fully specified for partial-power-down applications usingIoff. The Ioff circuitry disables the outputs, thuspreventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if eitherVCC input is at GND, both ports are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OE shall be tied to VCC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of thedriver.