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3.3-V Low-Voltage Quadruple FET Bus Switch with 5-V Tolerant Level Shifter


Package | PIN: PW | 14
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $1.53
10-24 $1.37
25-99 $1.28
100-249 $1.11
250-499 $1.02
500-749 $0.86
750-999 $0.71
1000+ $0.65


  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation On All Data I/O Ports
    • 5-V Input Down to 3.3-V Output-Level Shift With 3.3-VVCC
    • 5-V/3.3-V Input Down to 2.5-V Output-Level Shift With 2.5-VVCC
  • 5-V-Tolerant I/Os With Device Powered Up or Powered Down
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics
    (ron = 5 Ω Typical)
  • Low Input/Output Capacitance Minimizes Loading
    (Cio(OFF) = 4.5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 20 µA Max)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

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Texas Instruments  SN74CB3T3125PWR

The SN74CB3T3125 is a high-speed TTL-compatible FET bus switch with low ON-stateresistance (ron), allowing for minimal propagation delay. The device fullysupports mixed-mode signal operation on all data I/O ports by providing voltage translation thattracks VCC. The SN74CB3T3125 supports systems using 5-V TTL, 3.3-V LVTTL,and 2.5-V CMOS switching standards, as well as user-defined switching levels (seeTypical DC Voltage-Translation Characteristics).

The SN74CB3T3125 is organized as four 1-bit bus switches with separate output-enable(1OE, 2OE, 3OE,4OE) inputs. It can be used as four 1-bit bus switches or as one 4-bit busswitch. When OE is low, the associated 1-bit bus switch is ON, and the Aport is connected to the B port, allowing bidirectional data flow between ports. WhenOE is high, the associated 1-bit bus switch is OFF, and the high-impedancestate exists between the A and B ports.

This device is fully specified for partial-power-down applications usingIoff. The Ioff feature ensures that damaging currentwill not backflow through the device when it is powered down. The device has isolation during poweroff.

To ensure the high-impedance state during power up or power down,OE should be tied to VCC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of thedriver.