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SN74F109DR

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset

Packaging

Package | PIN: D | 16
Temp: C (0 to 70)
Carrier: Cut Tape
Qty Price
1-9 $0.64
10-24 $0.57
25-99 $0.53
100-249 $0.45
250-499 $0.42
500-749 $0.34
750-999 $0.27
1000+ $0.24

Features

  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

Texas Instruments  SN74F109DR

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and trying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54F109 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C.