SN74LV11ADR

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SN74LV11ADR

Triple 3-Input Positive-AND Gates

Packaging

Package | PIN: D | 14
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $0.56
10-24 $0.49
25-99 $0.45
100-249 $0.38
250-499 $0.34
500-749 $0.27
750-999 $0.20
1000+ $0.18

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Texas Instruments  SN74LV11ADR

These triple 3-input positive-AND gates are designed for 2-V to 5.5-V VCC operation.

The ’LV11A devices perform the Boolean function Y = A • B • C or Y = (A\ + B\ + C\)\ in positive logic.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.