SN74LV125ATPWR

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SN74LV125ATPWR

Quadruple Bus Buffer Gate With 3-State Outputs

Packaging

Package | PIN: PW | 14
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $0.26
10-24 $0.23
25-99 $0.21
100-249 $0.18
250-499 $0.16
500-749 $0.12
750-999 $0.09
1000+ $0.08

Features

  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V VCC Operation
  • Typical tpd of 3.8 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2.3 V at VCC = 5 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Texas Instruments  SN74LV125ATPWR

The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.