SN74LV126ANSR

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SN74LV126ANSR

Quadruple Bus Buffer Gates With 3-State Outputs

Packaging

Package | PIN: NS | 14
Temp: Q (-40 to 125)
Carrier: Cut Tape
Qty Price
1-9 $0.28
10-24 $0.25
25-99 $0.23
100-249 $0.19
250-499 $0.18
500-749 $0.14
750-999 $0.10
1000+ $0.09

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at
    VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at
    VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down
    Mode, and Back Drive Protection
  • Support Mixed-Mode Voltage Operation on All
    Ports
  • Latch-Up Performance Exceeds 250 mA per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Texas Instruments  SN74LV126ANSR

The ’LV126A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

These quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

The ’LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.