text.skipToContent text.skipToNavigation

SN74LV393ATPWREP

Enhanced Product Dual 4-Bit Binary Counters

Packaging

Package | PIN: PW | 14
Temp: S (-40 to 105)
Carrier: Cut Tape
Qty Price
1-9 $1.78
10-24 $1.59
25-99 $1.48
100-249 $1.29
250-499 $1.19
500-749 $1.00
750-999 $0.82
1000+ $0.75

Features

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 105°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 14.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down-Mode Operation
  • Dual 4-Bit Binary Counters With Individual Clocks
  • Direct Clear for Each 4-Bit Counter
  • Can Significantly Improve System Densities by Reducing Counter Package Count by 50 Percent

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Texas Instruments  SN74LV393ATPWREP

The SN74LV393A contains eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. This device is designed for 2-V to 5.5-V VCC operation.

This device comprises two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK)\ input. The device changes state on the negative-going transition of the CLK\ pulse. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The SN74LV393A has parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.