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SN74LV595AQPWRQ1

Automotive Catalog 8-Bit Shift Registers With 3-State Output Registers

Packaging

Package | PIN: PW | 16
Temp: Q (-40 to 125)
Carrier: Cut Tape
Qty Price
1-9 $0.85
10-24 $0.76
25-99 $0.70
100-249 $0.60
250-499 $0.55
500-749 $0.45
750-999 $0.36
1000+ $0.32

Features

  • Qualified for Automotive Applications
  • Customer-Specific Configuration Control Can Be Supported
    Along With Major-Change Approval
  • 2-V to 5.5-V VCC Operation
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Voltage Operation on All Ports
  • 8-Bit Serial-In, Parallel-Out Shift
  • Ioff Supports Partial-Power-Down Mode Operation
  • Shift Register Has Direct Clear

Texas Instruments  SN74LV595AQPWRQ1

The SN74LV595A is an 8-bit shift register designed for 2-V to 5.5-V VCC operation.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH' are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.