|Package | PIN:||SOP (NS) | 14|
|Temp:||Q (-40 to 125)|
- Operate From 1.65 V to 3.6 V
- Specified From –40°C to 85°C, –40°C to 125°C,
and –55°C to 125°C
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.1 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
- Ioff Support Live Insertion, Partial-Power-Down
Mode and Back-Drive Protection
- Latch-Up Performance Exceeds 250 mA
Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include
Testing of All Parameters.
Texas Instruments SN74LVC08ANSR
The SN54LVC08A quadruple 2-input positive-AND gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC08A quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.
The LVC08A devices perform the Boolean function Y = A B or Y = A\ + B\ in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.