SN74LVC112APWR

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SN74LVC112APWR

Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset

Packaging

Package | PIN: PW | 16
Temp: Q (-40 to 125)
Carrier: Cut Tape
Qty Price
1-9 $0.67
10-24 $0.59
25-99 $0.54
100-249 $0.46
250-499 $0.41
500-749 $0.32
750-999 $0.25
1000+ $0.21

Features

  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 3000-V Human-Body Model
    • 200-V Machine Model
    • 1500-V Charged-Device Model

Texas Instruments  SN74LVC112APWR

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.