|Package | PIN:||DCK | 5|
|Temp:||M (-55 to 125)|
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of 55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree(1)
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 6.7 ns at 3.3 V
- Low Power Consumption, 15-µA Max ICC
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over specified temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Texas Instruments SN74LVC1G86MDCKREP
This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G86 performs the Boolean function Y = A B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.