SN74LVC2G132DCTR

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SN74LVC2G132DCTR

Dual 2-Input NAND Gate with Schmitt-Trigger Inputs

Packaging

Package | PIN: DCT | 8
Temp: Q (-40 to 125)
Carrier: Cut Tape
Qty Price
1-9 $0.62
10-24 $0.55
25-99 $0.50
100-249 $0.43
250-499 $0.39
500-749 $0.30
750-999 $0.23
1000+ $0.20

Features

  • Available in Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.3 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
  • Support Translation Down (5V to 3.3V and 3.3V to 1.8V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Texas Instruments  SN74LVC2G132DCTR

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.