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SN74LVC32374AZKER

32-Bit Edge-Triggered D-Type Flip-Flop

Packaging

Package | PIN: ZKE | 96
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $3.24
10-24 $2.92
25-99 $2.72
100-249 $2.38
250-499 $2.23
500-749 $1.90
750-999 $1.60
1000+ $1.53

Features

  • Member of the Texas Instruments Widebus™ Family
  • Operates from 1.65V to 3.6V
  • Inputs Accept Voltages to 5.5V
  • Max tpd of 4.5 ns at 3.3V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Supports Mixed-Mode Signal Operation on All Ports (5-V Input and Output Voltages With 3.3-V VCC)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

Texas Instruments  SN74LVC32374AZKER

This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC32374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.