SN74LVT8986PM

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SN74LVT8986PM

3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) Tap Transceiver

Packaging

Package | PIN: PM | 64
Temp: I (-40 to 85)
Carrier: Partial Tray
Qty Price
1-9 $11.17
10-24 $10.39
25-99 $10.03
100-249 $8.76
250-499 $8.33
500-749 $7.67
750-999 $6.88
1000+ $6.86

Features

  • Members of the Texas Instruments (TI) Family of JTAG Scan-Support Products
  • Extend Scan Access From Board Level to Higher Level of System Integration
  • Three IEEE Std 1149.1-Compatible Configurable Secondary Scan Paths to One Primary Scan Path
  • Multiple Devices Can Be Cascaded to Link 24 Secondary Scan Paths to One Primary Scan Path
  • Simple (Linking Shadow) Protocol Is Used to Connect the Primary Test Access Port (TAP) to Secondary TAPs. This Single Protocol Is Used to Address and Configure the Secondary Scan Path.
  • LASP (8986) and ASP (8996) Can Be Configured on the Same Backplane Using Similar Shadow Protocols
  • Linking Shadow Protocols Can Occur in Any of Test Logic Reset, Run Test/Idle, Pause DR, Pause IR TAP States to Provide Board-to-Board and Built In Self Test
  • Bypass (BYP5-BYP0) Forces Primary to Configured Secondary Paths Without Use of Linking Shadow Protocols
  • Connect (CON2-CON0) Provides Indication of Primary-to-Secondary Paths Connections
  • Secondary TAPs Can Be Configured at High Impedance Via the OE Input to Allow an Alternate Test Master to Take Control of the Secondary TAPs
  • High-Drive Outputs (-32 mA IOH, 64 mA IOL) Support Backplane Interface at Primary Outputs and High Fanout at Secondary Outputs
  • While Powered at 3.3 V, Both Primary and Secondary TAPs Are Fully 5 V Tolerant for Interfacing 5 V and/or 3.3 V Masters and Targets
  • Package Options Include Plastic BGA (GGV) and LQFP (PM) Packages and Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacing

Texas Instruments  SN74LVT8986PM

The 'LVT8986 linking addressable scan ports (LASPs) are members of the TI family of IEEE Std 1149.1 (JTAG) scan-support products. The scan-support product family facilitates testing of fully boundary-scannable devices. The LASP applies linking shadow protocols through the test access port (TAP) to extend scan access to the system level and divide scan chains at the board level.

The LASP consists of a primary TAP for interfacing to the backplane IEEE Std 1149.1 serial-bus signals (PTDI, PTMS, PTCK, PTDO, PRTST) and three secondary TAPs for interfacing to the board-level IEEE Std 1149.1 serial-bus signals. Each secondary TAP consists of signals STDIx, STMSx, STCKx, STDOx, and STRSTx. Conceptually, the LASP is a gateway device that can be used to connect a set of primary TAP signals to a set of secondary TAP signals — for example, to interface backplane TAP signals to a board-level TAP. The LASP provides all signal buffering that might be required at these two interfaces. Primary-to-secondary TAP connections can be configured with the help of linking shadow protocol or protocol bypass (BYP5-BYP0) inputs.

Most operations of the LASP are synchronous to the primary test clock (PTCK) input. PTCK always is buffered directly onto the secondary test clock (STCK2-STCK0) outputs. Upon power up of the device, the LASP assumes a condition in which the primary TAP is disconnected from the secondary TAPs (unless the bypass signals are used, as shown in Function Tables 1 and 2). This reset condition also can be entered by asserting the primary test reset (PTRST) input or by using the linking shadow protocol. PTRST always is buffered directly onto the secondary test reset (STRST2-STRST0) outputs, ensuring that the LASP and its associated secondary TAPs can be reset simultaneously. The primary test data output (PTDO) can be configured to receive secondary test data inputs (STDI2-STDI0). Secondary test data outputs (STDO2-STDO0) can be configured to receive either the primary test data input (PTDI), STDI2-STDI0, or the cascade test data input (CTDI). Cascade test data output (CTDO) can be configured to receive either of STDI2-STDI0, or CTDI. CTDI and CTDO facilitate cascading multiple LASPs, which is explained in the latter part of this section. Similarly, secondary test-mode select (STMS2-STMS0) outputs can be configured to receive the primary test-mode select (PTMS) input. When any secondary TAP is disconnected, its respective STDO is at high impedance. Upon disconnecting the secondary TAP, the corresponding STMS holds its last low or high level, allowing the secondary TAP to be held in its last stable state.

The address (A9-A0) inputs to the LASP are used to identify the LASP. The position (P2-P0) inputs to the LASP are used to identify the position of the LASP within a cascade chain when multiple LASPs are cascaded. Up to 8 LASPs can be cascaded to link a maximum of 24 secondary scan paths to 1 primary scan path.

In a system, primary-to-secondary connection is based on linking shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states, other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address, position the LASP in the cascade chain that is being configured, and configuration of secondary TAPs via a serial bit-pair signaling scheme. When address and position bits received serially at PTDI match those at the parallel address (A9-A0) inputs and position (P2-P0) inputs respectively, the secondary TAPs are configured per the configuration bits received during the linking shadow protocol, then LASP serially retransmits the entire linking shadow protocol as an acknowledgment and assumes the connected (ON) status. If the received address or position does not match that at the address (A9-A0) inputs or position (P2-P0) inputs, the LASP immediately assumes the disconnected (OFF) status, without acknowledgment.

The LASP also supports three dedicated addresses that can be received globally (that is, to which all LASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the LASP to disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving LASPs. The DSA is especially useful when the secondary TAPs of multiple LASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the LASP to assume the reset condition. Receipt of the test-synchronization address (TSA) causes the LASP to assume a connect status (MULTICAST) in which PTDO is at high impedance, but the configuration of the secondary TAPs are maintained to allow simultaneous operation of the secondary TAPs of multiple LASPs. This is useful for multicast TAP-state movement, simultaneous test operation, such as in Run-Test/Idle state, and scanning of common test data into multiple like scan chains. The MULTICAST status may also be useful for concurrent in-system programming (ISP) of common modules. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states. Refer to Table 9 for different address mapping.

Alternatively, primary-to-secondary connection can be selected by asserting a low level at the bypass (BYP5) input. The remaining bypass (BYP4-BYP0) inputs are used for configuring the secondary TAPs. This operation is asynchronous to PTCK and is independent of PTRST and/or power-up reset. This bypassing feature is especially useful in the board-test environment because it allows board-level automated test equipment (ATE) to treat the LASP as a simple transceiver. When BYP5 is high, the LASP is free to respond to linking shadow protocols. Otherwise, when BYP5 is low, linking shadow protocols are ignored. Whether the connected status is achieved by use of linking shadow protocol or by use of bypass inputs, this status is indicated by a low level at the connect (CON2-CON0) outputs. Likewise, when the secondary TAP is disconnected from the primary TAP, the corresponding CON output is high. Each secondary TAP has a pass-through input and output consisting of SX2-SX0 and SY2-SY0, respectively. Similarly, the primary TAP also has a pass-through input and output consisting of PX and PY, respectively. Pass-through input PX drives the SY outputs of the secondary TAPs that are connected to the primary TAP. Disconnected secondary TAPs have their SY outputs at high impedance. Pass-through inputs SY2-SY0 of the connected secondary TAPs are logically ANDed and drive the PY output.