SN74LVTH273PWR

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SN74LVTH273PWR

3.3-V ABT Octal D-Type Flip-Flops With Clear

Packaging

Package | PIN: PW | 20
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $0.68
10-24 $0.61
25-99 $0.56
100-249 $0.48
250-499 $0.45
500-749 $0.36
750-999 $0.29
1000+ $0.26

Features

  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Typical VOLP (Output Ground Bounce)
        <0.8 V at VCC = 3.3 V, TA = 25°C
  • Support Unregulated Battery Operation Down to 2.7 V
  • Buffered Clock and Direct-Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Ioff Supports Partial-Power-Down-Mode Operation
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Texas Instruments  SN74LVTH273PWR

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.