SN74LVTH374DBR

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SN74LVTH374DBR

3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs

Packaging

Package | PIN: DB | 20
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $0.75
10-24 $0.67
25-99 $0.62
100-249 $0.53
250-499 $0.49
500-749 $0.40
750-999 $0.32
1000+ $0.29

Features

  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Support Unregulated Battery Operation Down to 2.7 V
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Texas Instruments  SN74LVTH374DBR

These octal flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The eight flip-flops of the ’LVTH374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.