text.skipToContent text.skipToNavigation

SN74SSTVF16857GR

14-Bit Registered Buffer With SSTL_2 Inputs and Outputs

Packaging

Package | PIN: DGG | 48
Temp: C (0 to 70)
Carrier: Cut Tape
Qty Price
1-9 $5.34
10-24 $4.81
25-99 $4.49
100-249 $4.02
250-499 $3.76
500-749 $3.27
750-999 $2.83
1000+ $2.77

Features

  • Member of the Texas Instruments Widebus™ Family
  • Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200
  • Pinout and Functionality Compatible With JEDEC Standard SSTV16857
  • 600 ps Faster (Simultaneous Switching) Than JEDEC Standard SSTV16857 in PC2700 DIMM Applications
  • Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated DIMM Load
  • Outputs Meet SSTL_2 Class I Specifications
  • Supports SSTL_2 Data Inputs
  • Differential Clock (CLK and CLK\) Inputs
  • Supports LVCMOS Switching Levels on the RESET\ Input
  • RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

Texas Instruments  SN74SSTVF16857GR

This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.

The SN74SSTVF16857 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.