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Flatlink 10-100MHz Transmitter


Package | PIN: DGG | 56
Temp: S (-10 to 70)
Carrier: Partial Tube
Qty Price
1-9 $4.65
10-24 $4.19
25-99 $3.91
100-249 $3.51
250-499 $3.27
500-749 $2.85
750-999 $2.47
1000+ $2.42


  • LVDS Display SerDes Interfaces Directly to LCD Display Panels with Integrated LVDS
  • Package Options: 8.1 mm × 14 mm TSSOP
  • 3.3-V Tolerant Data Inputs
  • Transfer Rate up to 100 Mpps (Mega Pixel Per Second)
  • Pixel Clock Frequency Range: 10 MHz to 100 MHz
  • Suited for Display Resolutions Ranging From HVGA up to HD With Low EMI
  • Operates From a Single 3.3-V Supply and 170 mW (Typical) at 75 MHz
  • 28 Data Channels Plus Clock In Low-Voltage TTL to 4 Data Channels Plus Clock Out Low-Voltage Differential
  • Consumes Less Than 1 mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered Inputs
  • ESD: 5000 V HBM
  • Support Spread Spectrum Clocking (SSC)
  • Compatible With all OMAP™ 2x, OMAP™ 3x, and DaVinci™ Application Processors

Texas Instruments  SN75LVDS83ADGG

The SN75LVDS83A Flatlink™ transmitter device contains four 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83A requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN75LVDS83A is characterized for operation over ambient air temperatures of –10°C to 70°C.

Alternative device option: The SN75LVDS83B is an alternative to the SN75LVDS83A for clock frequency range of 10 MHz to 135 MHz. The SN75LVDS83B is available in a smaller BGA package in addition to the TSSOP package.