text.skipToContent text.skipToNavigation


FlatLink 10-85MHz Serializer


Package | PIN: ZQL | 56
Temp: S (-10 to 70)
Carrier: Cut Tape
Qty Price
1-9 $6.13
10-24 $5.52
25-99 $5.15
100-249 $4.62
250-499 $4.31
500-749 $3.75
750-999 $3.25
1000+ $3.18


  • LVDS Display Serdes Interfaces Directly to LCD Display Panels with Integrated LVDS
  • Package: 4.5mm × 7mm BGA
  • 1.8V up to 3.3V Tolerant Data Inputs to Connect Directly to Low-Power,
    Low-Voltage Application and Graphic Processors
  • Transfer Rate up to 85Mpps (Mega Pixel Per Second);
    Pixel Clock Frequency Range 10MHz to 85MHz
  • Suited for Display Resolutions Ranging From HVGA up to HD With Low EMI
  • Operates From a Single 3.3V Supply and 148mW (typical) at 75MHz
  • 28 Data Channels Plus Clock In Low-Voltage TTL to 4 Data Channels
    Plus Clock Out Low-Voltage Differential
  • Consumes Less Than 1mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered Inputs
  • ESD: 5kV HBM
  • Support Spread Spectrum Clocking (SSC)

Texas Instruments  SN75LVDS83CZQLR

The SN75LVDS83C FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83C requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN75LVDS83C is characterized for operation over ambient air temperatures of –10°C to 70°C.