|Package | PIN:||AAJ | 324|
|Temp:||I (-40 to 85)|
- Quad-Channel Multi-Rate Transceiver
- Supports 10GBASE-KR, XAUI, and 1GBASE-KX
- Supports All CPRI and OBSAI Data Rates Up to
- Supports Multi-Rate SERDES Operation with Up to
10.3125 Gbps Data Rate on the High Speed Side
and Up to 5 Gbps on the Low Speed Side
- Differential CML I/Os on Both High Speed and Low
- Interface to Backplanes, Passive and Active
Copper Cables, or SFP+ Optical Modules
- Selectable Reference Clock per Channel with
Multiple Output Clock Options
- Loopback Capability on Both High Speed and Low
- Supports Data Retime Operation
- Supports PRBS, CRPAT, CJPAT, High-/Low-
/Mixed-Frequency Patterns, and KR Pseudo-
Random Pattern Generation and Verification,
- Two Power Supplies: 1.0-V, and 1.5 or 1.8-V
- No Power Supply Sequencing Requirements
- Transmit De-emphasis and Receive Adaptive
Equalization to Allow Extended Backplane/Cable
Reach on Both High Speed and Low Speed Sides
- Programmable Transmit Output Swing on Both
High Speed and Low Speed Sides
- Loss of Signal (LOS) Detection
- Supports 10G-KR Link Training, Forward Error
- Jumbo Packet Support
- JTAG; IEEE 1149.1/1149.6 Test Interface
- Industry Standard MDIO Clause 45 and 22 Control
- 65nm Advanced CMOS Technology
- Industrial Ambient Operating Temperature (40°C
- Power Consumption: 825 mW per Channel (Nominal)
- Device Package: 19-mm × 19-mm, 324-Pin PBGA,
Texas Instruments TLK10034AAJ
The TLK10034 is a quad-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode.
While operating in the 10GBASE-KR mode, the TLK10034 performs serialization of the 8B/10B encoded XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10034 performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs. The deserialized 64B/66B data is presented in 8B/10B format on the low speed side outputs. Link Training is supported in this mode as well as Forward Error Correction (FEC) for extended length applications.
While operating in the General Purpose SERDES mode, the TLK10034 performs 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10034 performs 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5Gbps to 5Gbps and the high speed side data rate can range from 1Gbps to 10Gbps. 1:1 retime mode is also supported but limited to 1Gbps to 5Gbps rates.
The TLK10034 also supports 1G-KX (1.25Gbps) mode with PCS (CTC) capabilities. This mode can be enabled via software provisioning or via auto negotiation. If software provisioFCBGAning is used, data rates up to 3.125 Gbps are supported.
Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors.
The TLK10034 provides flexible clocking schemes to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side. The device is also capable of performing clock tolerance compensation (CTC) in 10GBASE-KR and 1G-KX modes, allowing for asynchronous clocking.
The TLK10034 provides low speed side and high speed side loopback modes for self-test and system diagnostic purposes.
The TLK10034 has built-in pattern generators and verifiers to help in system tests. The device supports generation and verification of various PRBS, High, Low, Mixed, CRPAT long/short, CJPAT, and KR pseudo-random test patterns and square wave generation. The types of patterns supported on the low speed and high speed side are dependent on the operational mode chosen.
The TLK10034 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold.
In the 10GBASE-KR mode, the lane alignment for each channel is achieved through the standard XAUI lane alignment scheme. In the General Purpose SERDES mode the low speed side lane alignment for each channel is achieved through a proprietary lane alignment scheme. The upstream link partner device needs to implement the lane alignment scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved.
The four TLK10034 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization/deserialization ratios.
The low speed side of the TLK10034 is ideal for interfacing with an FPGA or ASIC capable of handling lower-rate serial data streams. The high speed side is ideal for interfacing with remote systems through optical fibers, electrical cables, or backplane interfaces. The TLK10034 supports operation with SFP and SFP+ optical modules, as well as 10GBASE-KR compatible backplane systems.