|Package | PIN:||GZZ | 201|
|Temp:||I (-40 to 85)|
- High-Performance, Low-Power, Fixed-Point TMS320C55x™ Digital Signal Processor (DSP)
- 3.33-/5-ns Instruction Cycle Time
- 300-/200-MHz Clock Rate
- 16K-Byte Instruction Cache (I-Cache)
- One/Two Instructions Executed per Cycle
- Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
- Two Arithmetic/Logic Units (ALUs)
- One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
- Instruction Cache (16K Bytes)
- 32K x 16-Bit On-Chip RAM That is Composed of Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
- 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
- 8M × 16-Bit Maximum Addressable External Memory Space
- 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
- Asynchronous Static RAM (SRAM)
- Asynchronous EPROM
- Synchronous DRAM (SDRAM)
- Synchronous Burst RAM (SBRAM)
- Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
- Programmable Low-Power Control of Six Device Functional Domains
- On-Chip Peripherals
- Six-Channel Direct Memory Access (DMA) Controller
- Three Multichannel Buffered Serial Ports (McBSPs)
- Programmable Analog Phase-Locked Loop (APLL) Clock Generator
- General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)
- 8-Bit/16-Bit Parallel Host-Port Interface (HPI)
- Four Timers
- Two 64-Bit General-Purpose Timers
- 64-Bit Programmable Watchdog Timer
- 64-Bit DSP/BIOS™ Counter
- Inter-Integrated Circuit (I2C) Interface
- Universal Asynchronous Receiver/Transmitter (UART)
- On-Chip Scan-Based Emulation Logic
- IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
- 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)
- 201-Terminal MicroStar BGA™ (Ball Grid Array) (GZZ and ZZZ Suffixes)
- 3.3-V I/O Supply Voltage
- 1.26-V Core Supply Voltage
(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).
TMS320C55x, DSP/BIOS, MicroStar BGA, C55x, eXpressDSP, Code Composer Studio, RTDX, XDS510, TMS320C54x, C54x, TMS320, TMS320C5000 are trademarks of Texas Instruments.
I2C bus is a trademark of Koninklijke Philips Electronics N.V.
All trademarks are the property of their respective owners.
Texas Instruments TMS320VC5502GZZ300
The TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.
The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.
The 5502 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is a 8-/16-bit parallel interface used to provide host processor access to 32K words of internal memory on the 5502. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included.
The 5502 is supported by the industry's award-winning eXpress DSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments. algorithm standard, and the industry's largest third-party network. The Code Composer Studio™ IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5502 is also supported by the C55x™ DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.