|Package | PIN:||DRC | 10|
|Temp:||M (-55 to 125)|
- Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
- VLDOIN Voltage Range: 1.1 V to 3.5 V
- Sink and Source Termination Regulator Includes
- Requires Minimum Output Capacitance of 20-µF
(Typically 3 × 10-µF MLCCs) for Memory
Termination Applications (DDR)
- PGOOD to Monitor Output Regulation
- EN Input
- REFIN Input Allows for Flexible Input Tracking
Either Directly or Through Resistor Divider
- Remote Sensing (VOSNS)
- ±10-mA Buffered Reference (REFOUT)
- Built-in Soft Start, UVLO, and OCL
- Thermal Shutdown
- Meets DDR and DDR2 JEDEC Specifications
- Supports DDR3, Low-Power DDR3, and DDR4
- 10-Pin VSON Package With Thermal Pad
- Supports Defense, Aerospace, and Medical
- Controlled Baseline
- One Assembly and Test Site
- One Fabrication Site
- Available in Military (–55°C to 125°C)
- Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability
Texas Instruments TPS51200MDRCTEP
The TPS51200-EP device is a sink and source double data rate (DDR) termination regulator specifically designed for low-input voltage, low-cost, low-noise systems where space is a key consideration.
The TPS51200-EP maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The TPS51200-EP supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, Low-Power DDR3, and DDR4 VTT bus termination.
In addition, the TPS51200-EP provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.
The TPS51200-EP is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –55°C to +125°C.