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Fully I2C Programmable 6-CH LCD Bias IC For All Size TV Including Gate


Package | PIN: RHA | 40
Temp: S (-40 to 150)
Carrier: Cut Tape
Qty Price
1-9 $2.82
10-24 $2.54
25-99 $2.36
100-249 $2.07
250-499 $1.94
500-749 $1.65
750-999 $1.39
1000+ $1.33


  • Enable / Disable
    • TPS65177: VI power cycle
    • TPS65177A: VI power cycle or EN-pin
  • 8.6-V to 14.7-V Input Voltage Range
  • Non-Synchronous Boost Converter (V(AVDD))
    • Integrated Isolation Switch
    • 13.5-V to 19.8-V Output Voltage (I2C)
    • 15-V Default Output Voltage
    • 4.25-A Switch Current Limit (I2C)
    • High Voltage Stress Mode (I2C)
  • Synchronous Buck Converter (V(HAVDD))
    • 4.8-V to 11.1-V Output Voltage (I2C)
    • 7.5-V Default Output Voltage
    • 1.7-A Switch Current Limit
    • High Voltage Stress Mode (I2C)
  • Non-Synchronous Buck Converter (V(IO))
    • 2.2-V to 3.7-V Output Voltage (I2C)
    • 2.5-V Default Output Voltage
    • 3-A Switch Current Limit
  • Synchronous Buck Converter (V(CORE))
    • 0.8-V to 3.3-V Output Voltage (I2C)
    • 1-V Default Output Voltage
    • 2.5-A Switch Current Limit
  • Positive Charge-Pump Controller (V(GH))
    • 20-V to 40-V Output Voltage (I2C)
    • 28-V Default Output Voltage
    • Temp. Compensation Offset 0-V to 15-V (I2C)
    • 4-V Default Offset (28 V to 32 V)
  • Negative Charge-Pump Controller (V(GL))
    • –14.5-V to –5.5-V Output Voltage (I2C)
    • –7.9-V Default Output Voltage
  • Gate Pulse Modulation (GPM)
    • Down to 0-V, 5-V, 10-V or 15-V (I2C)
    • 0-V Default Discharge Voltage
  • Temperature Compensation for V(GH)
  • Thermal Shutdown
  • I2C Compatible Interface
  • EEPROM Memory
  • 6-mm × 6-mm × 1-mm 40-Pin VQFN Package

Texas Instruments  TPS65177ARHAR

The TPS65177/A provides all supply rails needed by a GIP (Gate-in-Panel) or non-GIP TFT-LCD panel. All output voltages are I2C programmable.

V(IO) and V(CORE) for the T-CON, V(AVDD) and V(HAVDD) for the Source Driver and the Gamma Buffer, V(GH) and V(GL) for the Gate Driver or the Level Shifter. For use with non-GIP technology Gate Pulse Modulation (GPM) is implemented, for use with GIP technology the V(GH) rail can be temperature compensated. Furthermore a High Voltage Stress Mode (HVS) for V(AVDD) and V(HAVDD) and an integrated V(AVDD) Isolation Switch is implemented. V(CORE), V(HAVDD), V(GH), V(GL), GPM and the V(GH) temperature compensation can be enabled and disabled by I2C programming.

A single BOM (Bill of Materials) can cover several panel types and sizes whose desired output voltage levels can be programmed in production and stored in a non-volatile integrated memory.