|Package | PIN:||PWP | 20|
|Temp:||Q (-40 to 125)|
- 2-A Low-Dropout Voltage Regulator
- Available in 1.5 V, 1.8 V, 2.5 V, 3.3 V Fixed Output and Adjustable Versions
- Open Drain Power-On Reset With 100ms Delay (TPS752xxQ)
- Open Drain Power-Good (PG) StatusOutput (TPS754xxQ)
- Dropout Voltage Typically 210 mV at 2 A (TPS75233Q)
- Ultralow 75-µA Typical Quiescent Current
- Fast Transient Response
- 2% Tolerance Over Specified Conditions for Fixed-Output Versions
- 20-Pin TSSOP PowerPAD™ (PWP) Package
- Thermal Shutdown Protection
- DSP, FPGA Supplies
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Texas Instruments TPS75425QPWP
The TPS752xxQ and TPS754xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233Q, TPS75433Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
210 mV at an output current of 2 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The device is enabled when EN is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = +25°C.
The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage.
The TPS754xxQ has a power good terminal (PG) as an active high, open drain output for use with a power-on reset or a low-battery indicator.
The TPS754xxQ and TPS752xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS754xxQ and TPS752xxQ families are available in a 20-pin TSSOP (PWP) package.