|Package | PIN:||PZ | 100|
|Temp:||T (-40 to 105)|
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of 40°C to 110°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product Change Notification
- Qualification Pedigree
- 3.3-V and 5-V PCI bus signaling
- 3.3-V supply (core voltage is internally regulated to 1.8 V)
- Serial bus data rates of 100M bits/s, 200M bits/s, and 400M bits/s
- Physical write posting of up to three outstanding transactions
- Serial ROM interface supports 2-wire devices
- External cycle timer control for customized synchronization
- PCI burst transfers and deep FIFOs to tolerate large host latency
- Two general-purpose I/Os
- Fabricated in advanced low-power CMOS process
- Packaged in 100-terminal LQFP (PZ)
- PCI_CLKRUN\ protocol
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
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Texas Instruments TSB12LV26TPZEP
The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with the PCI Local Bus Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and 1394 Open Host Controller Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, and 400M bits/s serial bus data rates.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV26 device is compliant with the PCI Bus Power Management Interface Specification, per the PC 99 Design Guide requirements. TSB12LV26 device supports the D0, D2, and D3 power states.
The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided to buffer 1394 data.
The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface.
An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at PCI clock rates up to 33 MHz.