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32-Rail PMBus Power Sequencer and System Manager


Package | PIN: ZWS | 169
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $24.09
10-24 $22.40
25-99 $21.62
100-249 $18.89
250-499 $17.97
500-749 $16.54
750-999 $14.85
1000+ $14.80


  • Sequence, Monitor, and Margin 24 Voltage Rails Plus 8 Digital Rails
  • Monitor and Respond to OV, UV, OC, UC, Temperature, Time-Out, and GPI-Triggered Faults
  • Flexible Sequence-On and Off Dependencies, Delay Time, Boolean Logic, and GPIO Configuration to Support Complex Sequencing Applications
  • 4 Rail Profiles for Adaptive Voltage Identification (AVID) Voltage Regulator
  • High-Accuracy Closed-Loop Margining
  • Active Trim Function Improves Rail Output Voltage Accuracy
  • Advanced Nonvolatile Event Logging To Assist System Debugging
    • Single-Event Fault Log (100 entries)
    • Peak ValueLog
    • Black Box Fault Log to Save Status of All Rails and I/O Pins at the FirstFault
  • Easily Cascade Up to 4 Power Sequencers and Take Coordinated Fault Responses
  • Programmable Watchdog Timer and System Reset
  • Pin-Selected Rail State
  • PMBus 1.2 Compliant

Texas Instruments  UCD90320ZWST

The UCD90320 device is a 32-rail PMBusaddressable power sequencer and system manager in a compact 0.8-mm pitch BGA package.

The 24 integrated ADC channels (AMONx) monitor the power supply voltage, current, andtemperature. Eighty-four GPIO pins can be used for 8 digital monitor (DMONx), 32 power supplyenable (ENx), 24 margining (MARx), 16 Logical GPO, 32 GPI, cascading, and system function.

The 32 ENx pins and the 16 LGPOx pins can be configured to be active driven or open drainoutputs.

Nonvolatile event logging preserves fault events after power dropout. Black box fault logfeature preserves the status for all rails and I/O pins when the first fault occurs. The cascadingfeature offers convenient ways to manage up to 128 voltage rails through one SYNC_CLK pinconnection. Fault pin feature coordinates among cascaded devices to take synchronized faultresponses. The pin-selected rail states feature employs up to 3 GPIs to control up to eight user-defined power states. These states can implement system low-power modes as outlined in the (ACPI) specification.

For all available packages, see the orderable addendum at the