56-pin (DGG) package image

SN75LVDS82DGG 正在供货

FlatLink™ 接收器

等同于: SN75LVDS82DGGG4 该器件型号与上面所列的器件型号相同。您只能订购该器件型号的上述数量。

定价

数量 价格
+

其他包装数量 | 包装选项 这些产品完全相同,仅包装类型不同

SN75LVDS82DGGR 正在供货 custom-reels 定制 可提供定制卷带
包装数量 | 包装 2,000 | LARGE T&R
库存
数量 | 价格 1ku | +

质量信息

等级 Catalog
RoHS
REACH
引脚镀层/焊球材料 NIPDAU
MSL 等级/回流焊峰值温度 Level-2-260C-1 YEAR
质量、可靠性
和封装信息

包含信息:

  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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更多制造信息

包含信息:

  • 制造厂地点
  • 封装厂地点
查看

出口管制分类

*仅供参考

  • 美国 ECCN:EAR99

封装信息

封装 | 引脚 TSSOP (DGG) | 56
工作温度范围 (°C) 0 to 70
包装数量 | 包装 35 | TUBE

SN75LVDS82 的特性

  • 4:28 Data Channel Expansion at up to 1904 Mbps Throughput
  • Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
  • Four Data Channels and Clock Low-Voltage Differential Channels In and 28 Data and Clock Low-Voltage TTL Channels Out
  • Operates From a Single 3.3-V Supply With 250 mW (Typical)
  • 5-V Tolerant SHTDN Input
  • Falling Clock-Edge-Triggered Outputs
  • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Pixel Clock Frequency Range of 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard

SN75LVDS82 的说明

The SN75LVDS82 FlatLink™ receiver contains four serial-in, 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit.

These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS83B, over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 for 21-bit transfers.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×) the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).

The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user.

The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low-level on SHTDN clears all internal registers to a low level and places the TTL outputs in a high-impedance state.

The SN75LVDS82 is characterized for operation over ambient air temperatures of 0°C to 70°C.

定价

数量 价格
+

其他包装数量 | 包装选项 这些产品完全相同,仅包装类型不同

SN75LVDS82DGGR 正在供货 custom-reels 定制 可提供定制卷带
包装数量 | 包装 2,000 | LARGE T&R
库存
数量 | 价格 1ku | +

包装方式

您可以根据器件数量选择不同的包装方式,包括完整卷带、定制卷带、剪切带、管装或托盘。

定制卷带是从整盘卷带上剪下来的具有连续长度的剪切带,是一种可以对特定数量提供产品批次及生产日期跟踪的包装方式。根据行业标准,使用黄铜垫片在剪切带两端各连接一个 18 英寸的引带和尾带,以直接送入自动组装机。涉及定制卷带的 TI 订单将包含卷带费用。

剪切带是从整盘卷带上剪下来的特定长度的编带。根据所申请器件数量的不同,TI 可能会使用多条剪切带或多个盒子进行包装。

TI 通常会根据库存情况选择将管装托盘器件以盒装或者管装或托盘形式发货。所有器件均会按照 TI 内部规定的静电放电和湿敏等级保护要求进行包装。

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可提供批次和生产日期代码选项

您可在购物车中添加器件数量以开始结算流程,并查看现有库存中可选择批次或生产日期代码的选项。

了解更多信息