ADC32J45EVM

ADC32J45 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter Evaluation Module

ADC32J45EVM

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Overview

The ADC32J45 EVM demonstrates the performance of a low power dual 160Msps 14 bit ADC. It includes the ADC32J45 device, LMK04828 JESD204B clocking solution and TI voltage regulators to provide the necessary voltages. The input for the ADC is connected to a transformer input which can be connected to a 50 ohm single ended signal source. The clock reference input is provided via a transformer input and can be connected to a 50 ohm single ended clock source. The onboard LMK04828 can be used to generate the necessary JESD204B clocks. Register access is provided through the on board USB connection and a GUI.  For a complete evaluation system, TI also offers the TSW14J50 data capture card and High Speed Data Converter Pro Software.

  • Single 1.8V supply to simplify power requirements
  • Flexible input clock buffer with 1/2/4 divider to simplify clocking
  • On chip dither to improve SFDR
  • JESD204B data interface to simplify digital interface, compliant up to 3.2Gbps lane rates
  • Supports subclasses 0,1,2 for synchronization and compatibility
  • Pin compatibility with 12/14b and dual/quad devices
High-speed ADCs (>10MSPS)
ADC32J45 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter (ADC)
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Evaluation board

ADC32J45EVM – ADC32J45 Evaluation Module

Evaluation board

ADC32J45EVM-BDL – ADC32J45EVM + TSW14J50EVM Data Capture / Pattern Generator Bundle

GUI for evaluation module (EVM)

ADC3xxx GUI Installer (Rev. C) – SLAC667C.ZIP (196003KB)

TI's Standard Terms and Conditions for Evaluation Items apply.

Design files

ADC3xJxxEVM Design Package (Rev. A) SLAR094A.ZIP (11316 KB) ADC3xJxxEVM Design Package - PCB rev B SBAC206.ZIP (8685 KB) ADC32xxEVM Design Package - PCB rev B SBAC207.ZIP (6373 KB)

Technical documentation

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Type Title Date
More literature ADC32J45EVM EU Declaration of Conformity (DoC) Jan. 02, 2019
User guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) Aug. 24, 2018

Related design resources

Hardware development

EVALUATION BOARD
ADC34J45EVMADC34J45 Quad-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter Evaluation Module
TSW14J50EVMData capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-6.5Gbps
TSW14J56EVMData capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps
TSW14J57EVMData capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps
INTERFACE ADAPTER
TSW14J10EVMData Converter Evaluation Module to FPGA Platform FMC Adapter: 10 JESD204B Lanes up to 12.5Gbps

Software development

SUPPORT SOFTWARE
DATACONVERTERPRO-SWHigh-speed data converter pro software

Support & training

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