ADS6125EVM

ADS6125 12-Bit, 125-MSPS Analog-to-Digital Converter Evaluation Module

ADS6125EVM

Order now

Overview

The ADS6125EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS6125 device, a low power 12-bit 125 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a flexible environment to test the ADS6125 under a variety of clock, input and supply conditions.

The evaluation module also allows designers to use either a transformer coupled input into the ADC or an amplifier input based on the Texas Instruments‘ THS4509. While the ADC EVM comes with the THS4509, users can easily evaluate any of the footprint compatible ADC driving amplifiers such as the THS4508, THS4511, THS4520.

  • Transformer coupled analog input path
  • Transformer coupled clock input path
  • Amplifier path based on the THS4509
  • Configurable parallel output modes
  • Direct connection to TSW1100 High Speed ADC Capture Card
  • Separate analog and digital supply connections
High-speed ADCs (>10MSPS)
ADS6125 12-Bit, 125-MSPS Analog-to-Digital Converter (ADC) ADS6128 12-Bit, 210-MSPS Analog-to-Digital Converter (ADC) ADS6148 14-Bit, 210-MSPS Analog-to-Digital Converter (ADC) ADS61B29 12-Bit, 250-MSPS Analog-to-Digital Converter (ADC) ADS61B49 14-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

 

Clock buffers
CDCP1803 1:3 LVPECL Clock Buffer with Programable Divider

Order & start development

Evaluation board

ADS6125EVM-BDL – ADS6125EVM + TSW1400EVM Data Capture / Pattern Generator Bundle

Support software

TIGAR Support Files – SBAC120.ZIP (262219KB)

TI's Standard Terms and Conditions for Evaluation Items apply.

Design files

ADS61xxEVM Design Package - Board rev SLAR115.ZIP (1378 KB)

Technical documentation

star
= Top documentation selected by TI
No results found. Please clear your search and try again.
View all 3
Type Title Date
More literature ADS6125EVM EU Declaration of Conformity (DoC) Jan. 02, 2019
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008

Related design resources

Hardware development

EVALUATION BOARD
TSW1400EVMData Capture/Pattern Generator: Data Converter Evaluation Module With 8 LVDS Lanes up to 1.5Gbps
TSW1405EVMData Capture/Pattern Generator: Data Converter Evaluation Module With 8 LVDS Lanes up to 1.0Gbps
DAUGHTER CARD
HSMC-ADC-BRIDGEHigh Speed ADC to HSMC (Altera) Header Adaptor Card
INTERFACE ADAPTER
FMC-ADC-ADAPTERHigh Speed ADC to FMC (Xilinx) Header Adapter Card

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​

Videos