LMK04808BEVAL

Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.9 GHz VCO

LMK04808BEVAL

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Overview

The LMK04800 family is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode. 

The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

 

Features
  • Multi-mode: Dual PLL, single PLL, and clock distribution
  • Dual Loop PLLatinum PLL Architecture
      - PLL1
        > Holdover mode when input clocks are lost
          + Automatic or manual triggering/recovery
      - PLL2
        > Integrated Low-Noise VCO
  • 2 redundant input clocks with LOS
      - Automatic and manual switch-over modes
  • 50% duty cycle output divides, 1 to 1045 (even and odd)
  • LVPECL, LVDS, or LVCMOS programmable outputs
  • Precision digital delay, fixed or dynamically adjustable
  • 25 ps step analog delay control.
  • 14 differential outputs. Up to 26 single ended.
      - Up to 6 VCXO/Crystal buffered outputs
  • 0-delay mode
Clock jitter cleaners & synchronizers
LMK04808 Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO

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Evaluation board

LMK04808BEVAL/NOPB — Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.9 GHz VCO

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Technical documentation

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Type Title Date
* EVM User's guide LMK0480x Evaluation Board Instructions (Rev. B) Aug. 04, 2014
Certificate LMK04808BEVAL/NOPB EU Declaration of Conformity (DoC) Jan. 02, 2019
EVM User's guide LMK048xx Evaluation Board User's Guide Nov. 26, 2013
EVM User's guide LMK0480x Evaluation Board Instructions Jan. 27, 2012

Related design resources

Software development

APPLICATION SOFTWARE & FRAMEWORK
CLOCKDESIGNTOOL Clock Design Tool - Loop Filter & Device Configuration + Simulation
IDE, CONFIGURATION, COMPILER OR DEBUGGER
CODELOADER CodeLoader Software for device register programming

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