DDR Termination Regulator


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The LP2996 evaluation board is designed to provide the design engineer with a fully functional prototype system in which to evaluate the LP2996 in both a static environment and with a complete memory system. There are two versions of the board, and while identical in functionality they differ in the package implemented; This is the SO PowerPAD package.

  • Source and sink current
  • Low output voltage offset
  • No external resistors required
  • Linear topology
  • Suspend to Ram (STR) functionality
  • Low external component count
  • Thermal shutdown
  • Available in PSOP-8 package


  • DDR-I and DDR-II Termination Voltage
  • SSTL-2 and SSTL-3 Termination
  • HSTL Termination


DDR memory power ICs
LP2996-N 1.5A DDR termination regulator with shutdown pin for DDR2

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Evaluation board

LP2996MREVAL – DDR Termination Regulator

TI's Standard Terms and Conditions for Evaluation Items apply.

Technical documentation

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Type Title Date
* User guide AN-1268 LP2996 Evaluation Board (Rev. A) May 07, 2013
More literature LP2996MREVAL EU Declaration of Conformity (DoC) Jan. 02, 2019

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