Power Management Reference Design for Xilinx Virtex-6 FPGAs (1.8V @ 2.6A)
PMP5098
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Description & Features

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Description

The PMP5098 reference design uses four (4) TPS40400 PMBus synchronous buck controllers to regulate and control the Xilinx Virtex-6™ FPGA rails. The output voltages can be dynamically adjusted within a 400mV range with 4mV steps. Additional PMBus control includes: Fsw, ILIM, SS time, UVLO, Thermal Shutdown, ENABLE, PGOOD, UVP, OVP, and OCP modes. The design is ideal for applications that require having design flexibility for the Virtex 6™ four output voltages through PMBus programming, configuration, and control.

Features
  • AVS Capability- dynamically adjust Vo through PMBUS: 400mV range with 4mV step
  • PMBUS Configurability  of the power supply parameters
  • Differential voltage sensing
  • Differential inductor DCR current sensing
  • 200KHz-2MHz prog. fsw, pre-bias start up support 
  • Frequency synchronization, and upstream voltage rail tracking


  



Schematic/Block Diagram

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Test Data

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Design Files

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TI Devices (2)

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Part Number Name Product Family Sample & Buy Design Kits & Evaluation Modules
CSD16411Q3  25-V, N channel NexFET™ power MOSFET, single SON 3 mm x 3 mm, 15 mOhm  MOSFETs  Sample & Buy Not Available
TPS40400  3-V to 20-V, 30-A, synchronous buck controller with PMBus™, including Telemetry  Step-down (buck) regulators  Sample & Buy View Design Kits & Evaluation Modules

CAD/CAE symbols

Part # Package | Pins CAD File (.bxl) STEP Model (.stp)
CSD16411Q3 VSON-CLIP (DQG)| 8 Download Download
TPS40400 Download Download

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Technical documentation
User guide (1)
Title Type Size (KB) Date
PDF 368 09 Jun 2011
Design files (3)
Title Type Size (KB) Date
ZIP 33163 08 May 2014
PDF 36 09 Jun 2011
PDF 374 09 Jun 2011

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